1. Field of the Invention
The present invention relates to parallel analog-to-digital converters (ADCs) and more particularly to digital encoding techniques for reducing the output errors of an ADC.
2. Description of the Related Art
The objective of ADC circuits is to receive an analog signal and produce an error free digitized version of that analog signal. A well known ADC circuit is the parallel or flash ADC, which receives an analog signal to be digitized at an input node and compares its voltage to a set of reference voltages. For n bits of resolution in the ADC's digital output, a known voltage is applied to a ladder of 2.sup.n series resistors to provide reference voltages at the nodes between the resistors. Comparators, typically implemented with high gain amplifiers, receive respective reference voltages at one input and the analog input signal at another input to produce either a low output (binary 0) if the comparator's reference voltage is greater than the analog input, or a high output (binary 1) if the analog input is higher than the comparator's reference voltage. Ideally, the resulting digital comparator outputs, referred to as a thermometer code, are a series of binary 0s for comparators which receive reference voltages greater than the analog input signal, and a series of binary is for comparators which receive a reference voltage less than the analog input signal. The transition from binary 0s to 1s indicates the amplitude of the analog input signal.
To generate a digital output, the thermometer code is first applied to a 1-of-(2.sup.n -1) decoder that generates a 2.sup.n line output code with only one active output line, which corresponds to the binary 0-to-1 transition in the thermometer code. The decoder's active output selects and enables a single address in a 1-of-2.sup.n -to-Binary encoder that has a set of encoded n-bit standard Binary codes for each address. The n-bit standard Binary code and the corresponding address are matched. For example, if n=4 the first address, AO, has a binary code 0000, the second address, A1, has a binary code 0001, and so on to the sixteenth address, A15, having a binary code 1111. The encoder address selected provides the standard Binary code output of the ADC which corresponds to the strength of the analog input signal. The encoder is typically implemented using read only memory (ROM).
A common problem with the parallel ADC is that, when it is operated at high analog input slew rates, irregular comparator outputs may be produced due to timing skews between adjacent comparators, the analog input signal and the comparators' strobe signal. Comparator output irregularities result in more than one binary 0-to-1 transition in the thermometer code. This in turn causes more than one decoder output to be activated, which in turn causes multiple encoder addresses to be selected. The encoder output is typically the logical OR or the logical AND of these addresses, producing an ADC output that is an inaccurate digitized version of the input.
Several digital encoding methods exist which reduce the errors resulting from the conversion of the thermometer code to an n-bit Binary ADC output. The encoding methods operate by passing the decoder output through an encoder which has a set of error reducing n-bit codes at each input address that compensate for the possibility of receiving multiple binary 0-to-1 transition points from the comparators. The error reducing encoder output is then decoded to a standard Binary code which is the ADC's error reduced output.
One well known error reducing encoding method is the Gray code, which provides only a one bit change in the encoder codes of adjacent addresses. For example, adjacent addresses A2 and A3 have corresponding codes of 0011 and 0010, respectively. As another example, adjacent addresses A7 and A8 have corresponding codes of 0100 and 1100, respectively. The logical OR of any two Gray codes from adjacent addresses is thus always equal to one of the codes, resulting in an error in the Grey code decoder output of at most one in 2.sup.n parts (this is assuming that the error occurs at adjacent encoder input addresses). The n-bit Gray code encoder output is then converted into an n-bit standard Binary code through a decoder circuit to produce the ADC output. A problem with the Gray-to-Binary decoder circuit is that it takes several gate delays to convert the Gray code encoder output to standard Binary form, significantly slowing down the ADC's throughput rate. Also, the Gray code has limited error reduction capacity for errors that are not at adjacent encoder addresses.
Another encoding technique is the Quasi-Gray code, which is disclosed in Japanese Patent Application No. S60-171023, Kamoto et. al., Aug. 5, 1985. The Quasi-Gray code improves on the throughput rate of the Gray code by converting its encoder output to standard Binary code in only a single gate delay. The error reducing performance of the Quasi-Gray code, however, is limited for multiple binary 0-to-1 transition points separated by two or more encoder addresses. The modified Quasi-Gray digital encoding technique, disclosed in U.S. Pat. No. 4,975,698 to Kagey, Dec. 4, 1990, improves on the error correction performance of the Quasi-Gray code for simultaneous transition points separated by two or more encoder addresses. The modified Quasi-Gray code is the same as the Quasi-Gray code in all but the least significant bit position, which alternates in the same manner as the standard Binary code.